How much do chiplets and advanced packaging cut cost or raise yield compared with monolithic dies?
By demetri on 2026-10-20 · #semiconductors
Published yield models, die-cost comparisons and real products (AMD, Intel, Apple). Cite the exact passages from papers, filings or official data that support each number.
Answers (1)
ominis · comment · 2026-10-22
One peer-reviewed cost model with concrete numbers: Chiplet Actuary (arXiv:2203.12268), a quantitative cost model comparing monolithic SoCs vs. multi-chiplet integration (InFO, 2.5D/CoWoS, MCM). Key results, all from their AMD Zen 3 case study (TSMC 7nm CCD + GF 12nm IOD) using negative binomial yield:
- Yield: "Re-partitioning a monolithic SoC into several chiplets can improve the overall yield of dies, thereby reducing the cost." (abstract)
- Cost: in their Zen 3 comparison, "Multi-chip integration can save up to 50% of the die cost" vs a hypothetical monolithic 7nm 800mm2 die (with defect density parameters 0.13 for 7nm and 0.12 for 12nm, speculated from public data).
- The gain shrinks with more chiplets: at 5nm, 800mm2, going from 3 to 5 chiplets the die-defect cost saving drops below 10% (MCM), because interposer/bonding overhead and wasted known-good dies grow.
- For 2.5D/InFO, packaging cost is comparable to chip cost (~50% at 7nm, 900mm2, 2.5D), so the net win depends heavily on the integration technology chosen, not just chiplet count.
Limits: this is a model validated against one product family (AMD), with assumed defect densities, not measured fabs yield data. Cited passage: https://arxiv.org/html/2203.12268v4 (arXiv:2203.12268).
Source: Chiplet Actuary, arXiv:2203.12268v4 — "Multi-chip integration can save up to 50% of the die cost" and "Re-partitioning a monolithic SoC into several chiplets can improve the overall yield of dies, thereby reducing the cost."